The Mercury XU5 system-on-chip (SoC) module combines Xilinx's Zynq UltraScale+™ MPSoC-series device with fast DDR4 ECC SDRAM, eMMC flash, quad SPI flash, dual Gigabit Ethernet PHY, dual USB 3.0 and thus forms a complete and powerful embedded processing system.
Highlights
Built around Xilinx's Zynq Ultrascale+™ MPSoC
Two independent memory channels for PS (DDR4 ECC SDRAM) and PL (DDR4 SDRAM)
Up to 24 GByte/sec memory bandwidth
Offers PCIe® Gen3 x4, PCIe Gen2 x4, 2x USB 3.0 and 2x Gigabit Ethernet interfaces
Available in industrial temperature range
Two 168-pin Hirose FX10 connectors with 178 user I/Os
Not all features are available simultaneously – please check the documentation for any applicable constraints.
All specifications are subject to change without notice. Please verify component specifications with vendor’s datasheets.
Enclustra maintains an errata and revision history document for each product. Please also check the errata of the FPGA device and other components.
Product Selection Matrix
Product Code
MPSoC
DDR4 ECC SDRAM (PS)
DDR4 SDRAM (PL)
Temp. Range
Status
ME-XU5-2CG-1E-D10H1
XCZU2CG-1SFVC784E
1GB (no ECC)
512MB
0..+85°C
ME-XU5-2EG-1I-D11E
XCZU2EG-1SFVC784I
2GB
512MB
-40..+85°C
ME-XU5-3EG-2I-D11E
XCZU3EG-2SFVC784I
2GB
512MB
-40..+85°C
ME-XU5-4CG-1E-D11E-G12
XCZU4CG-1SFVC784E
2GB
512MB
0..+85°C
ME-XU5-4EV-1I-D11E
XCZU4EV-1SFVC784I
2GB
512MB
-40..+85°C
ME-XU5-4EV-1I-D11E-G12
XCZU4EV-1SFVC784I
2GB
512MB
-40..+85°C
ME-XU5-5EV-1E-D11E
XCZU5EV-1SFVC784E
2GB
512MB
0..+85°C
ME-XU5-5EV-2I-D12E
XCZU5EV-2SFVC784I
4GB
1GB
-40..+85°C
ME-XU5-5EV-2I-D12E-G12
XCZU5EV-2SFVC784I
4GB
1GB
-40..+85°C
ME-XU5-5EV-3E-D13E
XCZU5EV-3SFVC784E
8GB
2GB
0..+85°C
Custom Configurations
Click to view custom configuration options
TBC
TBC
TBC
Click on table to enlarge
1: This variant supports only half of the DDR4 bandwidth on the PS side (32-bit interface instead of 64-bit).
2: G1 assembly variants offered for migration purposes or for cases where the end application does not require GTR transceivers, but
instead more regular I/Os. It can be used when porting an existing design from Mercury ZX1 or ZX5 to Mercury XU5 SoC module.
Please refer to the user manual for details on assembly options and migration guidelines. This variant was referred to as “X1” variant in previous user manual versions.
Key:
Mass production
Sampling
Contact us
Minimum order quantities apply for custom module configurations. Please contact us.
We provide CNY prices with 13% VAT, please contact our China sales.
1+
30+
100+
1000+
10000+
1+
30+
100+
1000+
10000+
1+
30+
100+
1000+
10000+
我们在中国有分公司，提供人民币含税价，请联系kiddy.xu@enclustra.com
ME-XU5-2CG-1E-D10H
✔
350
308
273
247
208
407
358
317
287
242
375
330
292
264
223
ME-XU5-2EG-1I-D11E
✔
410
384
359
315
261
476
446
417
366
303
438
411
384
337
279
ME-XU5-3EG-2I-D11E
✔
624
585
548
487
405
725
679
636
565
470
668
625
586
520
433
ME-XU5-4CG-1E-D11E-G1
563
487
426
390
315
654
565
495
453
366
602
520
456
417
337
ME-XU5-4EV-1I-D11E
✔
783
662
573
525
432
909
769
665
610
502
837
708
612
562
462
ME-XU5-4EV-1I-D11E-G1
✔
783
662
573
525
432
909
769
665
610
502
837
708
612
562
462
ME-XU5-5EV-1E-D11E
899
761
658
605
493
1044
884
764
703
573
961
814
703
647
528
ME-XU5-5EV-2I-D12E
✔
1098
930
804
742
612
1275
1080
934
862
711
1174
994
860
794
655
ME-XU5-5EV-2I-D12E-G1
1098
930
804
742
612
1275
1080
934
862
711
1174
994
860
794
655
ME-XU5-5EV-3E-D13E
1249
1148
1061
933
791
1450
1333
1232
1084
918
1335
1227
1134
998
845
Click on table to enlarge
1: For non-preferred configurations, a minimum order quantity (MOQ) may apply if the products are not in stock – please get in touch for more details.
All prices are non-binding estimates – please use the enquiry form or contact us for definitive pricing and lead-time information.
Mercury Heat Sink
Large Heat Dissipation
High performance devices like the Xilinx Zynq Ultrascale+ MPSoC or Intel Arria 10 need cooling in most applications: always make sure the FPGA/SoC is adequately cooled.
The Mercury Heat Sink is an optimal cooling solution for Mercury and Mercury+ FPGA and SoC modules – it is low-profile and covers the whole module surface1.
The Mercury heatsink is provided as part of a heatsink accessory package including:
Heatsink body
Mounting material
Standard fan
Gap pad set
Design-in Kit – The Fast Way to the Market
The Enclustra Design-in Kits help shorten time-to-market for any Xilinx Zynq UltraScale+ MPSoC based application.
The design-in kits include everything you need to get started, also 2 AI example applications with all sources.
The examples are based on ResNet50 and Xilinx Vitis AI. The ready made binaries as well as the sources are packed with the box – as well as the extensive documentation how to build it yourself.
more
Base Boards
Select one of these base boards to get started with development straight out of the box.
Information contained on this web page is subject to change without notice. Actual product may differ in appearance from images shown on this web page.
For commercial reasons, this file is only available to Enclustra customers - if you're already a customer, simply fill in your name, company and email address below and we'll send you the file as soon as possible (usually within 24 hours).
If you're not currently a customer, we'd appreciate if you could provide a short message about your project requirements, and anything else we can assist you with.
Document Request
After filling out your contact details you will get an Email with a download link.
If you're not currently a customer, we'd appreciate if you could provide a short message about your project requirements, and anything else we can assist you with.
Sign up for the Enclustra Newsletter and save 10%
By signing up to receive our newsletter, as well as getting quarterly updates on what's happening at Enclustra, you'll receive a 10% discount, up to €50, off your next purchase of an FPGA hardware kit. Sign up now!
Mass production
Sampling
Contact us
Enclustra’s FPGA Manager™ solution allows for easy and efficient data transfer between a host and a FPGA over different interface standards like USB 2.0/3.0, Gigabit Ethernet and PCI Express. More>
Enclustra provides services covering the whole range of FPGA-based system development: From high-speed hardware or HDL firmware through to prototype production. More>
The Universal Drive Controller IP core enables the independent position and/or velocity control of up to 8 DC, BLDC or stepper motors directly from the SoC/FPGA. Optimized for superior performance and lowest total solution cost. More>
The Stream Buffer Controller IP Core implements a versatile Stream to Memory Mapped DMA bridge with 16 independent streams. The IP core allows data buffering in an external memory device to provide virtual FIFO capability with up to 4 GB memory size. More>
The Display Controller IP Core enables the easy addition of a display to existing or future FPGA designs, allowing the system designer to focus on the main application instead of dealing with display control issues. More>