Enclustra FPGA Solutions | FPGA Manager Ethernet SoC Edition | FPGA Manager Ethernet SoC Edition

FPGA Manager Ethernet SoC Edition

FPGA Manager Ethernet SoC Edition

FPGA Manager Ethernet SoC Edition

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Starting from EUR 18'300 / USD 19'300 / CHF 20'200


Enclustra’s FPGA Manager Ethernet SoC Edition allows for easy and efficient data transfer between a host and a FPGA over Ethernet TCP/IP.

The FPGA Manager Ethernet SoC Edition expands the existing FPGA Manager Ethernet Solution with a lossless TCP Ethernet link. The TCP stack is running on the processing system (PS) under embedded Linux.

The solution includes a host software library (a Windows DLL or Linux static library), and a daemon application for the FPGA/SoC. The user host application can communicate with the FPGA through a simple API consisting of simple read/write data commands hiding the complexity of the underlying protocols. Both streaming and memory-mapped access are supported.



  • High-throughput, plug & play Ethernet interface
  • Up to 100 MByte/sec data transfer rate
  • Windows and Linux Host/Embedded PCs supported
  • Supports free of charge AMD Xilinx AXI DMA IP-core
  • Reference design sources provided (Xilinx Block Design project)
  • Supports C, C++ and C# user applications
  • No recurring license fees
Enclustra Design Services

FPGA Manager Ethernet SoC Edition Evaluation

To evaluate the FPGA Manager Ethernet SoC Edition, Enclustra is providing a reference design. It's available for the Enclustra Mercury XU5 SoM (ME-XU5-2EG-1I-D11E) in combination with the Mercury+ PE1-200 base board.

The reference can easily be adapted to other Enclustra AMD Xilinx UltraScale+ modules. The evaluation license is valid for 3 month. The design stops working after 1 hour runtime and needs to be reset to run for another hour.


  • Complete and easy to use solution for communication between FPGA and host
  • No need for dealing with complexity of underlying protocols
  • Evaluation kits and reference design available
  • Highly configurable


  • Streaming data transfer between FPGA and host
  • Memory-mapped access to
    FPGA AXI bus
  • Up to 16 independent bidirectional data channels
  • Easy firmware Flash update capability
  • Tri-speed Ethernet (10/100/1000 Mbit/sec)


  • FPGA Manager SoC Daemon
    • .NET application (framework dependent deployment)
    • Example configuration file (used with the Reference Design)
    • User Manual documentation
  • FPGA Manager SoC Reference Design
    • Reference design top-level VHDL file (plain VHDL)
    • Xilinx Vivado™ project files (block design)
    • Example PetaLinux configuration
    • SD card image for a quick start on hardware
  • Enclustra Ethernet Host Library
    • Binary DLL
    • API header files
    • API User Manual

Site License Model

  • The license is granted to an "authorized site", meaning a single geographical location with radius < 5 km in which the licensee conducts business.
  • The licensed material can be used for unlimited projects and/or end products developed at the authorized site.

Product Selection Matrix

Product Code Description
EN-MGR-BASE1 Base license, 2 streaming channels
EN-MGR-OPT-XIL AMD Xilinx FPGA/SoC support
EN-MGR-OPT-ETH1G-PS2 PS Gigabit Ethernet Controller (GEM)
EN-MGR-OPT-WIN Windows Support (C/C++/.NET) (PCIe/Ethernet/USB)
EN-MGR-OPT-LIN Linux Support (C/C++) (PCIe/Ethernet)
EN-MGR-OPT-ADV2 Advanced features: 16 channels, multi-width and more

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1: Base license requires all listed options. Only option to choose from is between WIN or LIN.

2: Required for ETH1G-PS.

Target Applications

  • Test & Measurement
  • Image Processing
  • Smart Cameras
  • Software Defined Radio

Related Products

  • Enclustra Mars Family FPGA Modules
  • Enclustra Mars Family Base Boards
  • Enclustra Mercury Family FPGA Modules
  • Enclustra Mercury Family Base Boards



Support and Further Information

Information contained on this web page is subject to change without notice. Actual product may differ in appearance from images shown on this web page.