FPGA Manager PCIe

FPGA Manager PCIe

FPGA Manager PCIe

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Starting from EUR 7'200.– / USD 7'560.– / CHF 7'560.–

Overview

Enclustra’s FPGA Manager PCIe solution is optimized for Intel (Altera) and Xilinx FPGAs and allows for easy and efficient data transfer between a host and a FPGA over a PCI Express interface.

The solution includes a host software library (DLL/SO), a PCI Express driver, and a suitable IP core for the FPGA. The user host application can communicate with the FPGA through a simple API consisting of simple read/write data commands hiding the complexity of the underlying protocols. Streaming and memory-mapped accesses are supported.

 

Highlights

  • Over 700 MBytes/sec data
    transfer rate per direction
  • Low latency
  • Runs on Windows and Linux1
  • Supports C, C++, C#/.NET and MATLAB® user applications
  • Up to 4 GByte data transfer in a single DMA transfer
  • Infinite-length streaming transfers
  • Up to 128K DMA descriptors pre-fetching
  • Supports packet-based or stream-based data transfers
  • Configurable user datapath width (64-bit / 128-bit / 256-bit)
  • Supports TLP completion reordering
  • Power management capabilities
    on Windows (sleep/power-off and resume)

Benefits

  • Complete and easy to use solution for communication between FPGA and host
  • No need for dealing with complexity of underlying protocols
  • Runs straightforward on Windows and Linux1
  • Universal and friendly user space API on Windows and Linux1
  • Evaluation kits and reference design available
 

Features

  • Streaming data transfer between FPGA and host
  • Memory-mapped access to FPGA AXI bus
  • Up to 32 independent DMA channels (up to 16 in each direction)
  • Standard AXI Stream interface for user integration
  • Flexible and configurable
  • PCIe Gen 1 and Gen 2
  • ×1, ×2, ×4, ×8 lanes

Deliverables

  • FPGA Manager PCIe IP Core
    • VHDL source files (plain or encrypted, depending on product options)
    • Reference design
    • User manual
  • FPGA Manager PCIe DLL/SO
    • Binary DLL/SO
    • API header files
    • API user manual
  • FPGA Manager PCIe driver
    • Binary File
  • FPGA Manager PCIe Reference Design
    • Reference design top-level VHDL file (plain VHDL)
    • UCF / XDC / SDC constraint files (depending on product options)
    • Xilinx® ISE / Xilinx Vivado™ / Intel® Quartus® project files (depending on product options)
    • Top-level simulation test bench file (plain VHDL)
    • Top-level simulation ModelSim project file
    • Documentation
 

Site License Model

  • The license is granted to an "authorized site", meaning a single geographical location with radius < 5 km in which the licensee conducts business.
  • The licensed material can be used for unlimited projects and/or end products developed at the authorized site.

1: In beta phase. Ask for availability.

FPGA Manager Evaluation Kit

FPGA Manager IP Solution

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The FPGA Manager Evaluation Kit provides a full featured design platform to build communication centric applications for PCIe, Ethernet and USB 3.0. The kit provides an out-of-the box hardware platform with reference design to both speed your development time and enhance your productivity. It contains following components:
  • FPGA Manager IP Solution, Evaluation License
    • Runs on Windows
    • Supports up to 2 streams
    • Supports PCIe, Ethernet and USB 3.0
    • Encrypted VHDL
    • 1 hour time bomb
  • Reference design
  • Xilinx Kintex-7 based Mercury KX1 FPGA module (ME-KX1-160-1C-D10)
  • Mercury+ PE1-200 (ME-PE1-200-C) base board
  • Power supply
  • 2 hours support included1
  • Price: EUR 990 / USD 1112 / CHF 1068

1: Included only once per Site and Year.

Product Selection Matrix

Product Code Description
EN-MGR-BASE1 Base license, 2 streaming channels
EN-MGR-OPT-XIL Xilinx FPGA support
EN-MGR-OPT-ALT Intel FPGA support
EN-MGR-OPT-PCIE64 PCIe 64 bit support: PCIe Gen1 1X/2X/4X in Artix-7 & Cyclone V
PCIe Gen2 1X/2X/4X in Kintex-7 & Arria V
EN-MGR-OPT-WIN Windows Support (C/C++/.NET) (PCIe/Ethernet/USB)
EN-MGR-OPT-LIN Linux Support (C/C++) (PCIe/Ethernet)
EN-MGR-OPT-ADV Advanced features: 16 channels, multi-width and more
EN-MGR-OPT-HLL Higher-level language support: MATLAB (others upon customer request, e.g. Labview)

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1: The base package requires at least one of the Xilinx/Intel as well as one device unit options.

Target Applications

  • Test & Measurement
  • Image Processing
  • Smart Cameras
  • Software Defined Radio
 

Related Products

  • Enclustra Mars Family FPGA Modules
  • Enclustra Mars Family Base Boards
  • Enclustra Mercury Family FPGA Modules
  • Enclustra Mercury Family Base Boards


Ordering

 

Support and Further Information


Information contained on this web page is subject to change without notice. Actual product may differ in appearance from images shown on this web page.