Migrating DSP Projects to FPGAs

FPGA-based systems outperform DSP-based systems for signal processing applications while maintaining the ability to handle complex control tasks.

An increasing number of DSP designs are being migrated from digital signal processors to FPGA platforms. In many cases, this change is being driven by technical needs, such as greater processing power and increased flexibility. However, more practical considerations are also emerging, such as DSP chips reaching the end of their manufacturing lifecycle and becoming obsolete.

While FPGAs are widely recognized as an excellent choice for doing DSP, migrating to an FPGA platform can be a daunting task. This white paper outlines why this transition can still be worthwhile and offers guidelines on how to make each step of the process as pain-free as possible, all the way from designing the FPGA hardware platform to implementing the low-level DSP algorithm.

Why Choose an FPGA for DSP?

FPGAs are widely understood to offer immense parallel processing capability by leveraging pipelined processing architectures. However, they are equally capable of efficiently sharing resources to implement the same DSP function using only a tiny fraction of the FPGA resources (at the expense of a proportional reduction in throughput). By managing this tradeoff, FPGA designs can be heavily optimized to efficiently meet the throughput requirements of a wide range of DSP applications, from many GS/s all the way down to DC [1].

FPGA-based DSP designs also offer an important advantage in terms of reliability because they support a high degree of isolation between tasks. FPGA resources are typically dedicated to performing a specific function or task, whereas a processor-based system will share the same processor between many tasks, and the same memory between multiple threads. This means much more comprehensive design verification is feasible for the FPGA design, and long-term maintenance is simpler, particularly for more complex designs [2].

Hardware Migration

For hardware engineers new to FPGA development, migrating from a DSP processor to FPGA-based DSP hardware can be a significant undertaking. It can involve acquiring a new set of design skills and working with unfamiliar hardware, which adds risk to project schedules.

One way of significantly mitigating this risk is to use an FPGA module. In special cases where a module is not suitable, a custom FPGA platform can be developed.

Migrating to an FPGA Module

An FPGA or SoC module like the Enclustra Mercury+ XU9 combines all core parts needed to build a digital signal processing system (top: photograph, bottom: block diagram).

An FPGA module includes the main FPGA/SoC device, plus other key components such as power supplies, external memories (e.g. flash and DDR SDRAM) and communications interfaces (e.g. Ethernet, USB and SPI).

However, an FPGA module is much more than just the hardware. Enclustra modules are provided with extensive support materials and documentation, including schematics, pinouts, 3D models, net length tables, Linux BSPs, user manuals and reference designs. Therefore, the module-based approach is aimed at minimizing time and cost to market.

The module-based approach also offers an element of future-proofing because all modules belonging to the same product family are largely pin-compatible. Therefore, if hardware requirements change in the future, it is often possible to simply substitute a different FPGA module instead of redesigning and manufacturing new hardware.

Similarly, FPGA modules provide a level of independence from any specific FPGA vendor. For example, an AMD module can be interchanged with an Intel or Microchip module with relative ease. For more details about Enclustra’s portfolio of FPGA and SoC modules, please contact us to discuss your options.

Migrating to a Custom FPGA Platform

In some cases, a module is not a viable option. For instance, solutions requiring a special form factor, or additional or non-standard interfaces, may necessitate the development of a custom FPGA platform.

While this is undoubtedly a more complex task than using an off-the-shelf module, Enclustra has extensive experience in developing this type of hardware as a design service. Please contact us to discuss your requirements.

Algorithm Migration

Implementing a DSP algorithm in an FPGA is fundamentally different from doing it in a processor-based system. The main reason for this is that processors mostly execute instructions sequentially, whereas FPGAs mostly process data concurrently. When viewed from the outside, both systems may produce mathematically identical results, but internally they are completely different.

There is a common misconception that high-level synthesis (HLS) has eliminated the barrier between software and hardware, allowing a software engineer to develop FPGA algorithms using a software programming language. However, despite more than 40 years of HLS development, this is not true yet [3]. The main drawback of HLS remains poor Quality of Results (QoR), particularly with regards to timing performance. To improve QoR, developers must make heavy use of obscure vendor-specific pragmas and directives to guide the HLS compiler to describe better hardware. We already have HDLs that were designed specifically for hardware description, so they remain the best choice for producing high-quality DSP designs, at least for the foreseeable future.

Therefore, for a DSP engineer new to FPGA development, there are no easy shortcuts and the learning curve is steep. Similar to the hardware case, there are two main approaches to solving this migration challenge: off-the-shelf (IP) solutions and custom designs (or a combination of the two).

In either case, a major consideration when migrating any DSP algorithm from a processor-based system to an FPGA is the numerical representation of the internal signals, so this will be discussed first.

Fixed-Point Arithmetic in the FPGA

In DSP processors, both floating-point and fixed-point arithmetic are widely used. Each fixed-point operation (e.g. addition or multiplication) supports a constant bit-width, determined by the processor’s architecture. In FPGAs, efficient fixed-point arithmetic is used for the vast majority of DSP processing, and floating-point is reserved only for special cases. However, virtually any bit-width can be used for any fixed-point operation in order to meet dynamic range and precision requirements with optimal efficiency.

Therefore, a critical step in designing any FPGA-based DSP system is to determine suitable fixed-point representations for the signals at every node in the system. Specifically, that means:

Determining the signedness, number of integer bits and number of fractional bits at each circuit node.
Determining the rounding and saturation modes to use between any two consecutive circuit nodes where the fixed-point representation changes.

To do this, the fixed-point behavior must be properly modelled and analyzed.

The problem then is that modelling and analysis is best done in a high-level software language (such as Python or MATLAB), whereas the FPGA implementation is best done in a hardware description language (such as VHDL). Enclustra provides a free, open-source solution to bridge this gap: en_cl_fix. This code library enables the same fixed-point calculations to be easily implemented in different software/HDL languages.

Python:

# Add: c = a+b

c = cl_fix_add(a, a_fmt, b, b_fmt, c_fmt, FixRound.ConvEven_s, FixSaturate.Sat_s)

# Multiply: d = c*c

d = cl_fix_mult(c, c_fmt, c, c_fmt, d_fmt, FixRound.Trunc_s, FixSaturate.Warn_s)

VHDL:

-- Add: c = a+b

c <= cl_fix_add(a, a_fmt, b, b_fmt, c_fmt, ConvEven_s, Sat_s);

-- Multiply: d = c*c

d <= cl_fix_mult(c, c_fmt, c, c_fmt, d_fmt, Trunc_s, Warn_s);

In this way, the precise bit-true behavior of the fixed-point algorithm can be fully modelled and analyzed in software. Then, HDL implementation only needs to start after all the fixed-point number formats and rounding/saturation modes have been finalized. This shortens overall development time by doing initial design iterations in software instead of HDL firmware.

Writing both the software implementation as well as the HDL version may seem like duplicating efforts. However, the bit-true software model actually serves a dual purpose: it is also used for verification via a bit-true simulation flow. Input (stimulus) data is generated in Python/MATLAB and the corresponding output (response) data from the bit-true software model is saved to file. The HDL simulator then feeds the same stimulus into the HDL implementation and checks that the simulated HDL output perfectly matches the bit-true software’s response.

Therefore, the usually small effort of writing the software model pays significant dividends in terms of ease of design, analysis and verification. And this is all enabled using the free, open-source en_cl_fix library.

IP-Based DSP in the FPGA

The Universal DSP Library provides both continuous wave and pulse processing. It supports multi-channel signals (both in parallel and time-division multiplexed) and real or complex (IQ) data.

IP cores may be an attractive design migration option for DSP developers who have some FPGA experience but lack a library of DSP components implemented in HDL. Using IP cores can reduce time to market, as integrating verified components is typically faster than developing from scratch.

Enclustra’s Universal DSP Library is an IP product that aims to serve this purpose by providing HDL implementations of the most common DSP functions. Every component is available as unencrypted, vendor-independent VHDL source code. For AMD users, each component is also provided as an IP Integrator block, facilitating rapid development of signal processing chains in a graphical AMD Block Design.

The Universal DSP Library provides both continuous wave and pulse processing. It supports multi-channel signals (both in parallel and time-division multiplexed) and real or complex (IQ) data. However, this IP library is much more than just HDL source code. It comes with extensive support materials and documentation, including bit-true software models, reference designs and per-component documentation. For further details about the Universal DSP Library, please refer to the product page or contact us to discuss your requirements.

Custom DSP Algorithms in the FPGA

Most DSP designs include some amount of special project-specific processing that cannot be found in an off-the-shelf IP. In such cases, a custom solution must be developed.

In some cases, this means modifying or redeveloping a well-defined software algorithm into an efficient FPGA implementation. In other cases, it means starting from scratch and designing a new algorithm to efficiently meet a set of high-level requirements. Enclustra has extensive experience in providing these types of design services, and a long track record of successfully delivered FPGA-based DSP systems. Please contact us to discuss your project needs.

Conclusions

FPGAs are an excellent choice for a wide range of DSP applications, but migrating from a DSP processor to a new FPGA platform can be a daunting task. Off-the-shelf FPGA modules and IP can ease this migration and significantly reduce time and cost to market. When bespoke hardware or algorithms are needed, Enclustra can provide all the required know-how to take the project to a successful completion.