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UDP/IP Ethernet IP Core evaluation made easy

Nov 06, 2019

Enclustra UDP/IP Ethernet IP Core Evaluation Kit

For a speedy evaluation of our UDP/IP Ethernet IP Core, an evaluation kit is now available. The UDP/IP Ethernet IP Core Evaluation Kit provides a full featured design platform to build communication centric applications for Ethernet. The kit provides an out-of-the box hardware platform with reference design, to reduce development time and allow you to focus on your target application. The kit is comprised of:

  • UDP/IP Ethernet IP Core, Evaluation License
    • Encrypted VHDL
    • 1-hour time bomb
  • Mars AX3 FPGA module (MA-AX3-35-1I-D8)
  • Mars ST3 base board (MA-ST3)
  • Reference design
  • Two hours of support included1
  • Price: EUR 400 / USD 449 / CHF 440

1: Included only once per site and year

Xilinx Developer Forum The Hague: Connect with Enclustra

Oct 31, 2019

edge ai on enlcustra som

At the Xilinx Developer Forum (XDF) Enclustra presents the largest FPGA & SoC module portfolio. Enclustra's worldwide network translates that unique, cutting-edge FPGA expertise into easily usable added value for our customers in the form of a modular one-stop-shop solution. Take the chance and get all the latest FPGA and SoC news, lots of know-how and see the brand new and powerful Enclustra FPGA and SoC modules in action!

Take the next step and shorten your time-to-market and lower your development cost!
We look forward to meeting you in The Hague from November 12–13.

Enclustra at Xilinx Developer Forum XDF 2019

Connect • Learn • Share

Free seminar: Jump-start your AI based FPGA application

Oct 25, 2019

Free seminar: Jump-start your AI based FPGA application

It has never been so easy to jump-start AI applications. Thanks to FPGAs, like the Xilinx Zynq UltraScale+ MPSoCs, the power of AI can now also be used offline and on the edge. Learn how easy it is to realize your own AI application with the Xilinx edge machine learning flow.

Eager to learn? Klick on the link below and sign up for the free seminar, arranged by Enclustra and Avnet SILICA. Get all the details: More info

Free seminar: Jump-start your AI based FPGA application

Say hello to the Mercury+ XU9

Sep 26, 2019

mercury+ xu9

The newest member of our growing family of Xilinx Zynq UltraScale+ MPSoC based modules has arrived: Say hello to the Mercury+ XU9! It offers 20 multi-gigabit transceivers with data rates of up to 15 Gbit/sec each. To achieve the highest possible memory bandwidth, it is equipped with two memory banks: a 64-bit wide DDR4 SDRAM (up to 4 GBytes) connected to the PL and a 72-bit DDR4 ECC SDRAM (up to 8 GBytes) connected to the PS. Thus, the module achieves a memory bandwidth of up to 38.4 GByte/sec.

Enquire about the Mercury+ XU9 now.

Accelerate your development

Aug 29, 2019

AMZ, the Zurich based Formula Student Electric team, is using Enclustra modules already for the second season in a row in their motor inverters. Enclustra's Mercury ZX5 modules not only accelerate the car, but also the development: FPGA and SoC modules can cut the development time by half and lower total cost of ownership at the same time. Don't waste valuable time by reinventing the wheel but focus on your core competencies and get your product to market faster.

Read about the advanteges to use a module in the AMZ race car in the Circuit Cellar magazine. The article also provides technical details about the setup and the technology used in the car.

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