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We wish you a Merry Christmas

Dec 21, 2020

enclustra wishes a merry christmas

The year 2020 will soon be history – finally. Corona has shaken up the economy, workflows and communication. Many self-evident processes became laborious and complex overnight. Thanks to the great effort and high flexibility of everyone, fortunately most of the problems could be compensated.

Despite working from home and an increased coordination effort – and of course our loyal customers, that is you – Enclustra is able to close 2020 successfully.

We’d like to thank you for putting your trust in us. We look forward to a successful collaboration in 2021. The entire Enclustra team wishes you a merry Christmas, a happy new year and a prosperous and healthy 2021.

The Embedded Vision Platform

Oct 13, 2020

mercury+ xu8 mercury+ xu9
The Mercury+ XU8 (left) and the Mercury+ XU9

The fastest and easiest way to realize an embedded vision application is to use a System-on-Module.

Are you looking for a platform for your next embedded vision project? The search is over: The Enclustra Mercury+ XU8 and Mercury+ XU9 System-on-Modules (SOM) abstract the high complexity of the Xilinx Zynq UltraScale+ MPSoC EV devices and reduce time-to-market from years to months.

The SOMs integrate the Xilinx Zynq UltraScale+ MPSoC EV with fast DDR4 ECC SDRAM, eMMC flash, quad SPI flash, dual Gigabit Ethernet PHY and dual USB 3.0 on a tiny footprint of just 74 × 54 mm, and thus formin a complete and powerful embedded vision platform.

Start your project today: get in contact.

Virtual FIFO, the smart way

Sep 24, 2020

enclustra universal drive controller IP core solution
16 Streams – 4 GByte Size – DMA – Highly Configurable

The Stream Buffer Controller IP Core allows data buffering in an external memory to provide virtual FIFO capability.

The Stream Buffer Controller IP Core is optimized for FPGAs and implements a versatile Stream to Memory Mapped DMA bridge with up to 16 independent streams. The IP core allows data buffering in an external memory device to provide virtual FIFO capability with up to 4 GByte memory size. It provides an AMBA AXI4-Stream interface for each write and read data stream. A common memory-mapped master interface (AXI4 or Avalon) is provided to access the external memory device.

The IP core is highly configurable in terms of operation mode, buffer size and buffer address for each stream. The configuration is done over a memory-mapped slave interface, either by an embedded CPU, an FPGA Manager application or an application-specific stream configurator controller in VHDL. Get all the details: More info >

Motion control, in the fast lane

Sep 08, 2020

enclustra universal drive controller IP core solution
8 Drives – 200 kHz control rate – BLDC – DC – Stepper

The Universal Drive Controller IP Core makes the addition of drive control capabilities to FPGA designs a snap.

The modular Universal Drive Controller IP Core includes everything needed to control up to eight axes (i.e. motors) at control rates above 200 kHz, from the A/D converter interface to position, velocity and current controllers, position detection via encoder or resolver and control logic for power stages. DC, BLDC and 2- or 3-phase stepper motors are supported. Field-oriented control is available for brushless (BLDC) motors, and microstepping is supported for stepper motors.

A software API allows to access all functionality of the Universal Drive Controller without having to know the exact layout of the register bank and the meaning of each field within every register. The API is written in ANSI-C and can be ported to different CPU architectures easily or used in device drivers.

Thanks to the Evaluation Kit for Intel and Xilinx FPGAs it's a snap to add drive controller capabilities to any FPGA design. The kit provides a full featured design platform to build motion control applications. It provides an out-of-the box hardware platform with reference design, to reduce development time and allow you to focus on your target application — get all the details: More info >

Mercury XU5: the cost-effective UltraScale+ SoC module

Aug 27, 2020

enclustra fpga soc modules som design services
The Mercury XU5 module is based on the Xilinx Zynq UltraScale+ MPSoC and has a memory bandwidth of up to 24 GByte/sec.

The Mercury XU5 SoC module from Enclustra is an extremely powerful and cost-effective all-rounder. Based on the Xilinx Zynq UltraScale+ MPSoC, it features 6 ARM cores, a Mali 400MP2 GPU (EG/EV variants), up to 10 GByte of extremely fast DDR4 SDRAM, numerous standard interfaces, 178 user I/Os and up to 256,000 LUT4 equivalents.

The FPGA Board, with dimensions of just 56 × 54 mm, has 16 GByte eMMC flash memory as well as various standard interfaces, such as Gigabit Ethernet, USB 3.0, a display port, SATA and SGMII. Both the processing system and the FPGA matrix boast four PCIe Gen2/3 connections.

A System-on-Module (SOM) like the Mercury XU5 helps to reduce time-to-market and development risks. SOMs offer many advantages over chip-down designs. The high production quantity of off-the-shelf FPGA or SoC modules reduce their cost and at the same time provides a proven and reliable solution. Since different pin-compatible modules are available in the same form factor, a product can be easily equipped with a more powerful module if needed.

Thanks to the high functional density of the FPGA modules, the complexity of the base board is reduced, making it faster and less expensive to develop and produce. In combination with the Mercury+ ST1 or Mercury+ PE1 base boards, the Mercury XU5 constitutes a powerful development and prototyping platform that helps to reduce time-to-market by up to 12 month. Get all the details: More info >

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