Free seminar
Vision Projects with AMD Xilinx MPSoCs

Learn how to develop vision projects efficiently and successfully with AMD Xilinx MPSoCs

It's never been easier to design high-performance Vision applications. Thanks to SoCs with integrated FPGA fabric, like the AMD Xilinx Zynq UltraScale+ MPSoCs, the unprecedented processing power of this technology enables you to develop vision solutions in months instead of years.

In this free seminar, expert engineers from Enclustra and Avnet SILICA will show you how to successfully build a vision pipeline: connecting an image sensor to the FPGA, transferring the data to the CPU/PS, processing it in Linux and how to use the FPGA fabric as a machine vision accelerator.

Who should join

The seminar is aimed at all developers working with SoCs and FPGAs, in particular:

  • Project managers
  • Team leaders
  • Embedded software developers
  • System and software architects
  • FPGA/SoC developers
  • FPGA/SoC newbies


Time Topic
8:45-9:00 Registration
9:00-9:25 Welcome and introduction
9:25-10:45 System Design in Vision Projects
  • System partitioning
  • Managing system complexity
  • The Xilinx tool-flow on system level
  • Real-world examples
10:45-11:00 Break
11:00-12:00 Custom Video Algorithms in the FPGA
  • Algorithm acceleration
  • Real-time overlay rendering
  • Low-latency frame processing
12:00-13:00 Lunch
13:00-14:30 From Image Sensor to GStreamer Video Pipeline
  • Vivado reference design for the Enclustra Mercury+ XU8 SoM (equipped with the AMD ZU7EV MPSoC)
  • Introduction to the free Vitis Vision libraries
  • PetaLinux
    • Device tree
    • Video for Linux drivers
  • GStreamer live demos. From a simple video test pattern generator to an H265 encoded network video streaming application
14:30-14:45 Break
14:45-16:15 onsemi Image Signal Processor and Image Sensors
  • Connecting the ISP and image sensor to an MPSoC. Explaining the Vivado Design Suite for the Avnet Ultra96v2 Eval Kit equipped with the Dual Camera Mezzanine card
  • Live demo
Munich & Fribourg:
16:15-16:30 Round-up and Q&A
16:30-17:00 Meet the experts & networking
16:15-16:45Real-time Image Signal Processor for SoC/FPGA with Direct GPU Communication
16:45-17:00Round-up and Q&A
17:00-17:30Meet the experts & networking

All design files (Vivado + PetaLinux BSP) will be available for the attendees.

Dates and venues

When: October 18 2022
Where: Munich/DE @ Avnet Silica
Time: 08:45–17:00
Address: Avnet EMG GmbH
Im Technologiepark 2-8
85586 Poing
When: October 25 2022
Where: Fribourg/CH @ University of Fribourg
Time: 08:45–17:00
Address: Av. de l'Europe 20
1700 Fribourg