Preempt-RT Latency Benchmarking of the Cortex-A53 processor

ARMv8 processors are becoming more common in the industrial market – also thanks to theire use in recent FPGAs like the Xilinx Zynq UltraScale+ MPSoC. It is useful to understand how well these processors perform with Preempt-RT. In the presentation Preempt-RT Latency Benchmarking of the Cortex-A53 processor Paul Thomas from AMSC compares the CortexA53 utilized in the Xilinx Zynq UltraScale+ MPSoC processors in the Enclustra Mercury XU5 module with a Cortex-A9 based module.

Three different latency tests were performed: standard cyclictest latency, external hardware interrupt latency (as utilized by the I/O-subsystem) and Ethernet UDP latency. Analyzing the performance of a hardware interrupt can be tricky, the method of utilizing a timer with a capture function is detailed in the presentation.

Video: Application Acceleration with Xilinx UltraScale+ MPSoC module

For application acceleration FPGAs often offer the optimal solution in terms of performance, space, price and power consumption. Thanks to FPGA and SoC Modules like the Enclustra Mercury+ XU1 this especially holds true regarding time-to-market.

At Xilinx Developer Forum (XDF) Silicon Valley Enclustra showcased how a mathematically demanding problem can be solved efficiently in an MPSoC. The demo shows a Mercury+ XU1 module, that is based on the Xilinx Zynq UltraScale+ MPSoC, calculating the Mandelbrot fractal set in the FPGA fabric. The calculation in the FPGA/programmable logic is controlled and displayed from the Processing System running Ubuntu.

The demo shows how FPGAs can be integrated seamlessly into a CPU-based system to accelerate computational tasks. The FPGA fabric calculates 84 Billion 64x64 bit multiplications per second and displays up to over 100 frames per second at a resolution of 1920x1080 pixels (Full-HD).

For the next chance to see the power of FPGAs visit us at the Xilinx Developer Fair (XDF) Frankfurt, December 10^th 2018.

Get started with FPGA Manager- streaming, made simple.

Enclustra’s FPGA Manager IP solution is the Swiss Army Knife when it comes to data transfer between an FPGA and a PC. It allows for easy and efficient data transfer between a host and a FPGA over different interface standards like USB 2.0/3.0, Gigabit Ethernet and PCI Express.

Getting started with FPGA Manager is now even easier! Besides the Evaluation Kit the getting started guide helps you get up and productive in minutes. Even if it is written for Ethernet it also holds true for all other interfaces, thanks to the modular design of the FPGA Manager IP Solution.

Enclustra & hema at Vision 2018: decrease your development time

Visit Enclustra and hema electronic at Vision 2018, booth 1C83, to see how vision with FPGAs is done today! Enclustra is showing how you can decrease the development time of your next FPGA/SoC based design.

Mars PM3 Product Change Notification

The revision 5.2 of the Mars PM3 base board is not equipped any longer with the I2C GPIO expander SX1505I087TRT. This part is end-of-life and no compatible replacement component is available. See Known Issues and Changes for more information.

Design changes might be necessary when migrating designs from earlier revisions. The Patch Specification provides more information on signals around the I2C GPIO expander and possible connectivity options. The configuration of these signals cannot be performed during runtime any longer.