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EnTegra – your direct contact in the UK

Feb 01, 2021

lewis williams managing director entegra john owen technical director entegra
EnTegra Solutions is the official Enclustra partner in the UK

Lewis Williams (left), and John Owen have more than 20 years of experience.

Enclustra is happy to welcome EnTegra Solutions as its official reseller for Enclustra products in the UK. EnTegra has more than 20 years of experience in software and FPGA firmware development. EnTegra has always been more than just a reseller. As well as technical sales support, EnTegra has also developed example programs and full application suites to meet customer needs.

EnTegra is not only your first level contact for technical support: All of the products require technical expertise to ensure that the right product fits the application requirements before items are manufactured and shipped to the end user. That's exactly where the extensive expertise of EnTegra helps in finding the optimal solution.

You can contact EnTegra with any questions about the products at or send a message.

I2C what?

Jan 25, 2021

enclustra i2c application note
The I2C bus needs only 2 wires for bi-directional communication

A master can communicate with up to 1008 nodes at speeds of up to 5 Mbit/s.

The I2C (Inter-Integrated Circuit) protocol was invented 1982 by Philips. Thanks to it's simplicity and use of only 2 wires it is still very popular and widely used. Every Enclustra Module uses at least one I2C bus to communicate with several chips. Be it EEPROM, Real Time Clock (RTC) or clock generator: They are all connected via I2C to the FPGA.

The Enclustra I2C Application Note describes different possibilities to make use of the I2C bus to interface with the different I2C devices on Enclustra hardware. The Application Note gives an overview of the I2C bus in general and lists all the different devices present on Enclustra hardware and their capabilities (in terms of I2C communication).

Get all the details: Enclustra I2C Application Note

We wish you a Merry Christmas

Dec 21, 2020

enclustra wishes a merry christmas

The year 2020 will soon be history – finally. Corona has shaken up the economy, workflows and communication. Many self-evident processes became laborious and complex overnight. Thanks to the great effort and high flexibility of everyone, fortunately most of the problems could be compensated.

Despite working from home and an increased coordination effort – and of course our loyal customers, that is you – Enclustra is able to close 2020 successfully.

We’d like to thank you for putting your trust in us. We look forward to a successful collaboration in 2021. The entire Enclustra team wishes you a merry Christmas, a happy new year and a prosperous and healthy 2021.

The Embedded Vision Platform

Oct 13, 2020

mercury+ xu8 mercury+ xu9
The Mercury+ XU8 (left) and the Mercury+ XU9

The fastest and easiest way to realize an embedded vision application is to use a System-on-Module.

Are you looking for a platform for your next embedded vision project? The search is over: The Enclustra Mercury+ XU8 and Mercury+ XU9 System-on-Modules (SOM) abstract the high complexity of the Xilinx Zynq UltraScale+ MPSoC EV devices and reduce time-to-market from years to months.

The SOMs integrate the Xilinx Zynq UltraScale+ MPSoC EV with fast DDR4 ECC SDRAM, eMMC flash, quad SPI flash, dual Gigabit Ethernet PHY and dual USB 3.0 on a tiny footprint of just 74 × 54 mm, and thus formin a complete and powerful embedded vision platform.

Start your project today: get in contact.

Virtual FIFO, the smart way

Sep 24, 2020

enclustra universal drive controller IP core solution
16 Streams – 4 GByte Size – DMA – Highly Configurable

The Stream Buffer Controller IP Core allows data buffering in an external memory to provide virtual FIFO capability.

The Stream Buffer Controller IP Core is optimized for FPGAs and implements a versatile Stream to Memory Mapped DMA bridge with up to 16 independent streams. The IP core allows data buffering in an external memory device to provide virtual FIFO capability with up to 4 GByte memory size. It provides an AMBA AXI4-Stream interface for each write and read data stream. A common memory-mapped master interface (AXI4 or Avalon) is provided to access the external memory device.

The IP core is highly configurable in terms of operation mode, buffer size and buffer address for each stream. The configuration is done over a memory-mapped slave interface, either by an embedded CPU, an FPGA Manager application or an application-specific stream configurator controller in VHDL. Get all the details: More info >

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