Enclustra FPGA Solutions | Los Angeles Annual Seminar on FPGA / SoC | Los Angeles Annual Seminar on FPGA / SoC
Free seminar
Los Angeles Annual Seminar on FPGA / SoC with AMD

Learn about the latest technological innovations, practical solutions, tools and trends from the FPGA and SoC world

SoCs and FPGAs have proliferated in the past decade to the point of now being used in many of the systems we use in our daily life and those our industries and governments rely on. The development of SoCs and FPGAs systems has never been so much in demand.

In this free seminar made possible by Enclustra, expert engineers from Enclustra and LSF Design – a U.S. based embedded design firm – will present the latest technological innovations, practical solutions, tools and trends from the FPGA and SoC world that you can leverage in your next project.

For more information email us at tristan.martin@enclustra.com

Why join

  • Stay on top of your game with the latest technological innovations and trends from the FPGA and SoC world.
  • Exchange and get inspired. Network with other engineers working in the same field.
  • Connect with partners including design service companies, system-on-module and FPGA / SoC suppliers.

Who should join

  • Hardware and FPGA/SoC developers
  • Embedded software developers
  • System and software architects
  • Technical engineering manager

Schedule

Time Topic
8:00-8:45 Registration and Continental Breakfast
8:45-9:00 Opening note
9:00-9:45 Can you double your FPGA clock frequency and reduce the compilation time by 10X at the same time?
  • UCLA pioneered Vivado and Vitis HLS tools.
  • HLS breakthroughs: AutoBridge for high-frequency FPGA and RapidStream for faster compilation.
  • Both innovations won Best Paper Awards in FPGA'21 and FPGA'22, are open-source, and provide 2X clock speed increase and 7-10X faster compilation.
9:45-10:30 Multiproject/-product design strategy with FPGA SOM
  • Benefits of a multiproject/-product design strategy
  • Technology requirements
  • Implications to design flow
  • First steps
10:30-10:45 Unveiling of the demos

Low latency video demos

  • The demo compares the performance and resource usage of 3 different implementatoins of a video processing pipeline: Software, High Level Synthesis (HLS) and hand optimized VHDL.

Versal AI Edge demo

  • VEK280 Low-Latency DPU Benchmark Demo

High-Level Synthesis Demo

  • Layout-Guided Compilation and System Assembly for FPGA
10:45-11:15 Coffee & networking break
11:15-12:00 Efficient FPGA-based DSP up to GS/s
  • Traditional DSP design challenges
  • Parallel DSP – Handling sample rates above the clock frequency
  • Bit-true design approach

BONUS: includes Enclustra’s fixed-point & bit-true Python & HDL libraries for a cohesive step-by-step design and co-simulation process

12:00-13:00 Pizza or Deli Lunch and Networking
13:00-13:45 Key Considerations in FPGA-based Vision Systems
  • Optimizing video processing algorithms for FPGA implementation
  • Efficient bring-up of video and vision designs
  • Implications to design flow
  • AI, and when AI on FPGA makes sense

BONUS: includes application notes and firmware/software files for easy implementation of key IPs for your video applications (OpenGL ES on Mali GPU, VCU core, MIPI-CSI1/2/3, DisplayPort, and HDMI)

13:45-14:00 Coffee & networking break
14:00-14:45 The Versal™ AI Edge series (by AMD Xilinx)
  • What is an adaptive compute acceleration platform?
  • The Versal™ AI Edge product overview and roadmap
  • The Zynq UltraScale+ RFSoC product overview and roadmap
14:45-15:30 SOC Module Use in an Embedded Sonar Transmitter
  • Choosing an SOC Module for Embedded Applications
  • Sonar Application in an SOC overview
  • Enclustra Build Environment for Linux
  • Remote Host to FPGA Application Interfaces
15:30-15:45 Closing note
15:45-18:00 Happy hour and networking
18:00 End of event

Date and location

When: September 26, 2023
Where: Luxe Sunset Boulevard Hotel
11461 Sunset Blvd.
Los Angeles, CA 90049 .

Locations, Dates, and Agenda

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Click on the event to see the agenda.