Free seminar
Jump-start your AI based FPGA application

Learn how easy it is to realize your own AI application with the Xilinx edge machine learning flow

We'd like to invite you to this free seminar, arranged by Enclustra and Avnet SILICA, on FPGA-based AI applications.

It has never been so easy to jump-start AI applications. Thanks to FPGAs, like the Xilinx Zynq UltraScale+ MPSoCs, the power of AI can now also be used offline and on the edge. Be it image detection and classification, pattern or voice recognition for manufacturing, health care, automotive or financial services: the combination of an Enclustra SoC Module together with the Xilinx Machine Learning (ML) Suite that provides users with the tools to develop and deploy Machine Learning applications for Real-time Inference make it a snap to integrate AI in your application.

During this event, expert engineers from Avnet SILICA and Enclustra will give an introduction to AI and machine learning, and explain concepts, tools and realization on FPGAs. Based on the Enclustra Mars XU3 Xilinx Zynq UltraScale+ MPSoC Module it is shown how to implement a vision system that is recognizing fruits, even with minimal VHDL and FPGA know-how.

Take the opportunity to benefit from the experience of the Avnet SILICA and Enclustra engineers. For all participants we do offer an AI starter kit for a special price of only CHF 349.-1 (regular price over CHF 500.-).


Who should join

The seminar is aimed at all developers working with SoCs and FPGAs, in particular:

  • Embedded software developers
  • System and software architects
  • FPGA/SoC developers
  • FPGA/SoC newcomers
  • Project managers
  • Team leaders


8:45-9:00 Registration
9:00-9:25 Welcome and introduction
9:25-10:00 Introduction to artificial intelligence
10:00-10:30 Introduction to machine learning on FPGAs
10:30-10:45 Break & Table show
10:45-11:15 Xilinx Deep Learning Solutions
11:15-12:00 Keras/TensorFlow ResNet50 Training: Building a «Fruit Recognizer» on the Enclustra Mars XU3 SOM
12:00-13:00 Lunch
13:00-13:30 Integration of the Deep Learning Processing Unit in Vivado
13:30-14:15 Xilinx DNNDK: From a Tensor Flow net to the DPU Firmware
14:15-14:30 Break & Table show
14:30-15:00 Programming Model: The DPU API
15:00-15:30 Lausanne: Introduction of the Embedded Systems Laboratory Winterthur: Direct communication between FPGA and GPU using Frame Based DMA (FDMA)
15:30-16:00 Round-up, questions and answers
16:00-16:30 Table show & meet the experts

Time and places:

When: November 19th, 2019   When: November 21th, 2019
Where: EPFL Lausanne   Where: ZHAW Zürcher Hochschule für Angewandte Wissenschaften Winterthur
Room: Building Odyssee (ODY)
Room -1 0020
  Room: TP 408
Time: 08:45–16:30   Time: 08:45–16:30
Address: Route Cantonale
1015 Lausanne
, Switzerland
  Address: Technikumstrasse 9
8401 Winterthur
, Switzerland
Cost: Free   Cost: Free
Language: English   Language: English


1: Limited to one (1) kit per person. Special offer is valid until January 31, 2020. Price excluding shipping. Configuration: Mars XU3 (MA-XU3-2CG-1E-D10), Mars ST3 (MA-ST3) including Enclustra heat sink, accessory kit (ACC-BASE-USB2.0) and camera.