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At FPGA Conference Europe 2025 in Munich, Dr. Harry Commin, Lead FPGA/SoC Firmware Engineer at Enclustra, delivered an advanced technical session: “Doubling RFSoC ADC Rate from 5 Gsps to 10 Gsps.”

In this expert-level talk, Dr. Commin demonstrates how to digitally interleave three ADCs on an Zynq™ UltraScale+™ RFSoC to achieve a 10 Gsps effective sampling rate, without relying on complex analog circuitry. The presentation includes practical results from a recent Enclustra research project on AMD RFSoC, showcasing the approach’s real-world viability and performance.

If you missed FPGA Conference Europe 2025, here’s your chance!

Join our live webinar on September 30, 2025, at 17:00 CET / 11 EST where Dr. Harry Commin will present the same complex topic “Doubling RFSoC ADC Rate from 5 Gsps to 10 Gsps” — breaking it down in a clear, practical way and answering your questions live. Register here!

If you're working on wideband data acquisition, software-defined radio, or advanced RF applications, this session offers valuable technical knowledge and implementation guidance directly from the lab.

Questions after reading? Contact us at webinars@enclustra.com - we welcome technical discussions.