Display Controller IP core meets SDSoC
Our Universal Display Controller IP core allows easy integration of display control capabilities into an FPGA design, using various resolutions and interfaces, with minimal resource usage. Integration of the IP core is now even easier, as we've released a board support package for Xilinx SDSoC, including a reference design for the Mars ZX3 SoC module and Mars EB1 base board, a platform optimised for video applications.
Evaluation kit for motion control
Accurately set lock times for high and low-side switches in just a few second or PWM and control frequencies of a few hundred Kilohertz without any jittering: all this is possible thanks to our Universal Drive Controller IP Core , which supports DC, BLDC and 2 and 3-phase stepper motors. With the BLDC evaluation kit it couldn't be any easier to test the BLDC variant of the IP core. In addition to an evaluation license for the Universal Drive Controller IP Core, the kit includes a Mars ZX3 SoC module, a Mars PM3 base board, an FMC-DR2 power electronics card and a Maxon BLDC motor ( EC-max 30 with MR encoder ). If you want to know more about the inside and performance of the Unversal Drive Controller IP Core: check out the Universal Drive Controller IP Core Overview document.
For a cost-optimisation project in the field of industrial sensors in the security industry, we recently completed work which allows communication with sensors over power supply lines. An FPGA takes care of the channel encoding and decoding, and slots into the existing application seamlessly. Using this technique, the sensors can be connected via a two-wire connection, instead of the previous four-wire connection. Nifty.
Check out our design services offerings for more information.
Evaluate FPGA Manager - for free
Whether it’s writing configuration data, reading out measurement data, or streaming video, communication with a host PC is a part of many FPGA-based applications. This requires that the gap between the two very different worlds of VHDL programming and software development is bridged, ideally in such a way that both VHDL developer and software programmer can work within their areas of expertise without having to get deep into foreign technical territory.
FPGA Manager is a solution which brings all of these requirements together: an intuitive VHDL interface, a simple software interface, and all interfacing needs in between taken care of; interfaces such as USB 3.0, Gigabit Ethernet and PCI Express are all supported using one software API.
We're offering a free evaluation version of FPGA Manager upon request, for selected combinations of our FPGA modules and base boards.
Mercury+ PE1 base board, now in 3 variants
Our Mercury PE1 base board is now the Mercury+ PE1 base board - this transformation, however, hasn't required any shape-shifting. At first glance it's the same PCIe base board as before, but it's now offered in 3 different variants: the PE1-200, PE1-300, and PE1-400. The keen-eyed reader will also notice the third 168-pin Hirose connector, which means the board now supports FPGA and SoC modules in the Mercury+ form factor, which have 3 connectors, as well as Mercury modules with 2 connectors. The additional I/Os can be put to use with an FMC high pin-count add-on board, available on the PE1-300, or via two FMC low pin-count connectors, as on the PE1-400.
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