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Get ready for the Xilinx Zynq UltraScale+ module

Sep 13, 2016

Enclustra Mercury+ XU1 Xilinx Zynq UltraScale+ module

Our very first Xilinx Zynq UltraScale+ SoC module, the Mercury+ XU1, just went into production and we're very excited to get our hands on it. The module combines Xilinx's Zynq UltraScale+ MPSoC-series device with fast DDR4 ECC SDRAM, eMMC flash, quad SPI flash, dual Gigabit Ethernet PHY, dual USB 3.0, an RTC and 294 user I/Os in a package smaller than a credit card (74 × 54 mm).

If you'd like to get a headstart on a design based around the XU1, the user manual and reference design are good to go; just drop us a line to obtain them.

The Mercury+ KX2 has arrived

Aug 29, 2016

Enclustra Mercury+ KX2 Xilinx Kintex-7 module

The first Mercury+ KX2 prototypes have arrived - and they look rather good. It's our first FPGA module in the new Mercury+ form-factor, which adds a third 168-pin Hirose FX10 connector to the standard two found on Mercury modules. This doesn't come at the cost of increased size, though - the module is still a petite 74 × 54 mm.

The Mercury+ KX2 is based on the Xilinx® Kintex®-7 family. The compact module, which boasts 216 user I/Os and many standard interfaces, is equipped to handle even the most demanding of applications, with a high memory bandwidth of up to 12.5 GByte/sec. The module’s 216 user I/Os, 2 GByte DDR3L SDRAM and 64 MByte quad SPI flash combine to form a truly high-performance processing unit. The Mercury+ KX2 is equally well-suited for high-end digital signal processing, communications and networking, and high-speed I/O applications.

A myriad of interfacing options are also available: 8 MGTs with a data transfer rate of up to 10.3125 Gbit/sec, PCIe® Gen2 x8, dual Gigabit Ethernet, and USB 2.0. The module is available in both commercial and industrial temperature ranges, and needs just a single 5-15 V supply for operation.

Click through for more info.

Mercury+ PE1: 3D STEP model available

Aug 19, 2016

Enclustra Mercury+ PE1 base board 3D STEP file

The Mercury+ PE1 base board together with one of our Mercury FPGA or SoC modules form a complete ready-to-use platform. To ease the mechanical design-in Enclustra now offers also a 3D model in STEP format. Just click on «Mercury PE1 STEP 3D Model» in the right panel on the Mercury+ PE1 page to request it.

Display Controller IP core meets SDSoC

Aug 02, 2016

Our Universal Display Controller IP core allows easy integration of display control capabilities into an FPGA design, using various resolutions and interfaces, with minimal resource usage. Integration of the IP core is now even easier, as we've released a board support package for Xilinx SDSoC, including a reference design for the Mars ZX3 SoC module and Mars EB1 base board, a platform optimised for video applications.

Evaluation kit for motion control

Jul 22, 2016

Enclustra Universal Drive Controller IP Core

Accurately set lock times for high and low-side switches in just a few second or PWM and control frequencies of a few hundred Kilohertz without any jittering: all this is possible thanks to our Universal Drive Controller IP Core , which supports DC, BLDC and 2 and 3-phase stepper motors. With the BLDC evaluation kit it couldn't be any easier to test the BLDC variant of the IP core. In addition to an evaluation license for the Universal Drive Controller IP Core, the kit includes a Mars ZX3 SoC module, a Mars PM3 base board, an FMC-DR2 power electronics card and a Maxon BLDC motor ( EC-max 30 with MR encoder ). If you want to know more about the inside and performance of the Unversal Drive Controller IP Core: check out the Universal Drive Controller IP Core Overview document.

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