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PCIe now even easier to use with FPGA Manager

Jul 03, 2018

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The FPGA Manager PCIe communication solution is even more flexible now. The FPGA Manager IP core now connects to the PCIe hard macro from Xilinx and Intel in the user design, thus making its configuration by the user much easier. This also simplifies and speeds up the porting of an application onto another FPGA or host.

In all other aspects, everything remains the same: the FPGA Manager IP Solution from Enclustra makes it easier than ever to write configuration data, export measurement data and stream video data. Besides PCIe, the solution also features Ethernet and USB interfaces. Experience the solution first-hand with the FPGA Manager Evaluation Kit.

How to connect a high level programming language to an FPGA

Jun 28, 2018

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Our FPGA/SoC Development Engineer Matthias Frei held a speech at the FPGA Kongress in Munich on the Universal connection between an FPGA and a high-level programming language. In the speech he breaks down the reasons, requirements and challenges when linking an FPGA to a high-level language. Additionally, he explains why a standard solution makes sense and what the FPGA Manager IP Solution is.

If you missed the speech, go visit Enclustra’s Publication & Talks site and read more about it: Publications

Xilinx UltraScale+ MPSoC as application accelerator

Jun 26, 2018

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At the Embedded Computing Conference, our FPGA/SoC Development Engineer Matthias Frei spoke on the Xilinx UltraScale+ MPSoC as application accelerator. In the speech he introduces the Mandelbrot set and its calculation as well as how to best map it onto the Enlcustra Mercury+ XU1 MPSoC.

Detailed information can be found in the following link: Publications

Reaching for the stars

Jun 25, 2018

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The KIPP nanosatellite from Kepler Communications measures approximately 10×10×30 cm and is equipped with an FPGA module from Enclustra. The module was a key piece of the puzzle for realizing a high level of functionality with low power consumption in such a small design

If you want to track the whereabouts of the Enclustra module in space, simply click this link to find out.

The Mercury XU5 has arrived

Jun 19, 2018

mercury xu5 Enclustra’s latest SoC module based on Xilinx Zynq® UltraScale+ has just arrived from assembly. The Mercury XU5 features more direct interfaces to the FPGA fabric, in addition to a Gigabit Ethernet connection as well as up to 2 GByte DDR4 SDRAM. The module also has up to 8 GByte DDR4 ECC SDRAM connected directly to the processing system and a Gigabit Ethernet interface. Both the processing system and the FPGA matrix boast an up to four lanes PCIe® Gen2/3 connection.

In addition to six ARM cores, the 56 × 54 mm module features a Mali400MP2 GPU, an H.264/H.265 video codec (for EV variants), 16 GByte eMMC flash memory, USB 3.0 and 178 User I/Os.

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