Enclustra">Enclustra
IP Cores
Motion Control
| IP Core | Description | Status | |
| Universal Drive Controller |  |
This IP core enables the independent position and/or velocity control of up to 8 DC, BLDC or stepper motors directly from the FPGA. |
Available in Q3 2010 |
| Advanced Velocity Estimator |  |
This IP core provides highly accurate velocity estimation from quadrature encoder signals over a wide velocity range by making use of FPGA-specific features. | Available in Q2 2010 |
SoPC / Embedded Computing
| IP Core | Description | Status | |
| TFT Display Controller |  |
This IP core enables the easy integration of TFT displays into FPGA-based systems. | Available now! |
Module-Specific IP Cores
| IP Core |
Description | Available for |
Status |
| FX2 USB Light IP for Saturn SX1 |
This IP enables a memory-mapped connection between a Saturn SX1 FPGA module and a host PC via high-speed USB. The IP consists of the FPGA IP core (netlist), Windows/Linux drivers, a well-documented API, a reference design as well as several host PC software examples. | Saturn SX1-1800 Saturn SX1-3400 |
Available now! |
ClustraBus IP
ClustraBus is a powerful, platform-independent Interconnect system that offers all the advantages of the most common SoPC bus systems (Avalon, PLB, Wishbone) without suffering from their major disadvantages. ClustraBus comprises a fully connected crossbar interconnect, as well as various bridges and links.
A wide variety of functionalities (external memory contollers, SPI/I2C master, FPGA-to-FPGA link, etc.) are available as IP cores with the ClustraBus interface, in addition to the Interconnect-specific blocks.
Enclustra would be happy to assist you in the design and implementation of your ClustraBus system!
Further Information
Please contact us.