Enclustra">Enclustra

Mercury CA1

Altera Cyclone IV E FPGA Module

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Mercury CA1 FPGA Module Mercury CA1 FPGA Module (front)
Mercury CA1 FPGA Module (back)

Overview

The Mercury CA1 module offers high-performance yet low cost Altera Cyclone IV FPGAs in conjunction with standard interfaces like USB 2.0 and Gigabit Ethernet.

With its powerful standard interfaces, the many LVDS capable I/Os, the large DDR2 SDRAM and the many hardware multipliers it is equally suited for digital signal processing, networking, high-speed I/O as well as SoPC applications utilizing the Altera Nios II soft processor.

Highlights

  • Features the latest Altera low-cost FPGA family
  • FTDI-based USB 2.0 High-Speed interface
  • Gigabit Ethernet PHY for high-bandwidth/low-latency networking
  • Smaller than a credit-card
  • Requires only a single supply voltage (5..16V)

Benefits

  • Vast parallel processing power for DSP applications (up to 200 multipliers at 260 MHz = 52 GMAC/s)
  • High-bandwidth data I/O thanks to the large number of available LVDS pairs
  • Simple and low-cost integration thanks to standard interfaces (USB, Gigabit Ethernet), single supply voltage and 2.5V / 3.3V power outputs
  • Simplified carrier board design (typically 4 layers)
  • Many IP cores are available from Altera, Enclustra and 3rd parties
 

Features

  • Altera Cyclone IV E FPGA
  • Small form factor (56 x 54 mm, dual 168-pin Hirose FX10 connectors)
  • 25 differential pairs and 98 single-ended user I/Os or 146 single-ended user I/Os (168 with custom configuration)
  • Up to 16 MB SPI Flash
  • Up to 256 MB DDR2 SDRAM
  • FTDI USB 2.0 High-Speed interface
  • Gigabit Ethernet PHY
  • High-power 8A core power supply

Module Architecture

Mercury CA1 Module ArchitectureClick image to enlarge

Product Selection Matrix

Mercury CA1 Product Selection Matrix

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Custom module configurations are available starting at 30 pcs order quantity. Please contact us.

Pricing

Mercury CA1 Pricing

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Reference Design

Mercury CA1 Qsys Reference Design

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The Mercury CA1 reference design consists of the following deliverables:

  • Precompiled FPGA configuration bitstream containing Qsys system featuring the following functional blocks:
    • Nios II CPU
    • DDR2 SDRAM controller
    • SPI and I2C masters, UART (FTDI), JTAG UART
    • Gigabit Ethernet MAC
    • Timer, GPIO
  • Console-based demo applications (including source code and SDK workspace)
    • DDR2 / SPI Flash memory tests
    • Ethernet / I2C bus / UART access
  • Documentation (also explaining how to customize and generate the Qsys system).

Please contact us via email for availability information.

Target Applications

  • Digital Signal Processing
  • Video Processing
  • Audio Processing
  • Motion Control
  • Software Defined Radio
  • Communications
  • Embedded Computing
  • Networking
  

Related Products

  • Enclustra Mercury Starter Base Board more

Ordering

 

Support and Further Information


Information contained in this web page is subject to change without notice. Actual product may differ in appearance from images shown on this web page.